1. Field of the Invention
The present invention relates to electronic circuits and systems. More specifically, the present invention relates to intermediate frequency amplifiers used in communications receivers.
2. Description of the Related Art
Power consumption is a critical consideration in the design and operation of electronic circuits and systems, particularly receivers used in communications systems. Conventionally, Class A amplifiers are used in communication receivers. Class A amplifiers use a single conductivity type transistor. In order to provide a signal current to a load, a large amount of direct (DC) current is required. This is due to the fact that in Class A amplifiers, the maximum load signal current is limited to the DC bias current. In push-pull operation, the load signal current is limited to twice the DC bias current. This is effectively the result of symmetric operation of two Class A stages in parallel. The load signal current is supplied by equal and opposite signal currents from the two Class A amplifiers in a push-pull action. Thus, the DC bias current for the push-pull amplifier can be one-half the DC bias current of the Class A amplifier to produce the same load signal current. As an example of this, if the load signal current is +I, this is generated by having the signal current of the upper class A PNP amplifier increase by +i/2, and the signal current of the lower Class A NPN amplifier decrease by +i/2, thereby creating the push-pull action.
Unfortunately, Class A amplifiers consume a considerable amount of power to achieve current performance requirements for noise and third order intercept (distortion intermodulation products).
Hence, a need remains in the art for an improved amplifier design offering lower power consumption operating at intermediate (IF) frequencies from baseband to 150 megahertz.
The present invention uses Class AB (push-pull) amplifiers, one in a higher voltage configuration and one in a lower voltage configuration, to achieve a high intercept at low power as well as a low noise figure. This complementary technology allows for higher performance at lower power.
In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for shifting a level of the input signal; and a third circuit for amplifying the input signal. In the illustrative embodiment, the third circuit includes first and second transistors Q3 and Q4 connected in a push-pull configuration. The first transistor Q3 is of a first type and the second transistor Q4 is of a second type. In the specific illustrative embodiment, the first and second transistors Q3 and Q4 are connected to form a Class AB push-pull amplifier.
The teachings of the present invention are illustrated in a differential amplifier having first and second symmetrical circuits. The first circuit includes a first terminal for receiving a first differential input signal; an arrangement for shifting a level of the first differential input signal; and a circuit for amplifying the first differential input signal. The amplifying circuit including first and second transistors Q3 and Q4 connected in a push-pull configuration. The second circuit includes a second terminal for receiving a second differential input signal; an arrangement for shifting a level of the second differential input signal; and a circuit for amplifying the second differential input signal. The circuit for amplifying the second differential input signal includes third and fourth transistors Q6 and Q5 connected in a push-pull configuration. An arrangement is included for coupling the first and second circuits.
In the illustrative embodiment the first and second transistors Q3 and Q4 are connected as class A amplifiers in a push-pull configuration to form a Class AB amplifier. Likewise, the third and fourth transistors Q6 and Q5 are connected as Class A amplifiers in a push-pull configuration to form a Class AB amplifier. In this embodiment, the first and third transistors Q3 and Q6 are connected as Class A amplifiers and the second and fourth transistors Q4 and Q5 are connected as Class A amplifiers. However, in an alternative embodiment, the first and third transistors Q3 and Q6 are connected as Class AB amplifiers and the second and fourth transistors Q4 and Q5 are connected as Class AB amplifiers.
The present invention provides good IP3 (third order intermodulation product) performance, low noise figure and low power consumption with an ideal (e.g. 50 ohm) characteristic impedance. These advantages are afforded by the fact that truly complementary NPN and PNP devices are used. As a result, the Class AB action of a push-pull architecture can be extended to frequency ranges beyond what has been achievable up to this point in time. This allows for numerous applications to be addressed as well as higher frequency ranges.